Chapter 11 Core Concepts and Terms
11.1 STM32L5: GTZC and subcomponents
TrustZone Security Controller (TZSC)
11.4 Embedded Protocol Analysis
11.5 Lifecycle Configurations
11.7 Flash Protections
System Design: Security Gates and System Security Controllers
11.8 System Security Components
11.9 System Security Design
System Design: Security Gates and System Security Controllers
11.10 Heap
11.11 Stack
Arm Architecture: Execution Modes and Privilege Levels
Arm Architecture: General-Purpose registers, special-purpose registers
11.12 Trustzone: Periphery
System Design: Security Gates and System Security Controllers
11.13 Implementation Defined Attribution Unit
11.14 Security Attribution Unit
IDAU and SAU: Security attribution
11.15 TrustZone-M core components
non-secure callable security attribute
11.16 Nonsecure function calls
11.17 Secure function calls
11.19 Interworking
11.20 Arm Registers
Arm Architecture: General-Purpose registers, special-purpose registers
11.23 Arm Privilege Levels
11.24 Arm Memory System
11.25 Vector Table
11.26 Arm Exception System
additional floating point context
STM32L5: TrustZone Illegal Access Controller (TZIC)
Arm Architecture: Execution Modes and Privilege Levels